A typical wireless communications device includes a memory, a processor cooperating with the memory, and a wireless transceiver cooperating with the processor for transmitting and receiving transmissions. The memory may store data to be processed or program code for execution by the processor. As computational demands on the typical wireless communications device have increased, the speed of the processor may be incremented to increase performance. Another approach to increasing wireless communications device performance is to reduce the time taken by the processor to access the memory, i.e. reducing memory access time.
An approach to reducing memory access time is to provide several types of memory, each with a different memory access time, for storing data. For example, the memory types may include long-term memory and short-term memory, for example, a cache. More specifically, the cache, which has a relatively quick access time, may be used to store data that is frequently accessed. Once the data is stored in the cache, future use can be made by accessing the cached copy rather than re-fetching or re-computing the original data, so that the average access time is shorter. On the other hand, the long-term memory is typically substantially larger than the cache but also includes a substantially greater memory access time.
Physically, within the typical wireless communications device, the processor and memory are typically separated, i.e. off-chip. In other words, the processor and memory are coupled together via a communication line, typically a data communications bus. In certain applications, this communications line between the processor and the memory presents a potential security risk to the computer system. For example, an unauthorized user may eavesdrop on the communications line in an attempt to perceive transmitted data from the memory, or the unauthorized user may compromise the memory and data stored therein.
An approach to this potential security risk is to encrypt ail data transmitted on this communications line between the memory and the processor. For example, as disclosed in U.S. Pat. No. 6,523,118 to Buer, a computing system includes a processor, a memory subsystem storing encrypted data, and a secure cache controller coupled between the memory and the processor. When the processor needs data stored in the memory subsystem, the processor communicates with the secure cache controller, which requests the encrypted data from the memory subsystem and subsequently decrypts the data for the processor. A potential drawback to this design is the decrease in device performance since the processor no longer directly accesses the memory subsystem.